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agilent HBCU-5710R 1000base-t small form pluggable low voltage (3.3 v) electrical transceiver over category 5 unshielded twisted pair cable data sheet description the HBCU-5710R electrical transceiver from agilent offers full duplex throughput of 1000 mb/s by transporting data over unshielded twisted pair category 5 cable with 5-level pam (pulse amplitude modulation) signals. the agilent 1000base-t module takes signals from both the twisted pair category 5 cable and the serdes interface. pin count overhead between the mac and the phy is minimized, and gigabit ethernet operation is achieved with maximum space savings. features ? designed for industry-standard msa-compliant, small form factor pluggable (sfp) ports compatible with ieee 802.3:2000 custom rj-45 connector with integrated magnetics link lengths at 1.25 gbd: up to 100 m per ieee802.3 low power, high performance 1.25 gbd serdes integrated in module single +3.3 v power supply operation auto-negotiation per ieee 802.3:2000 clause 28 (1000base-t) and clause 37 (1000base-x) applications switch to switch interface switched backplane applications file server interface related products hfbr-5601: 850 nm +5 v gigabit interface converter (gbic) for gigabit ethernet hfbr-53d5: 850 nm +5 v 1x9 optical transceiver for gigabit ethernet hfbr-5710l: 850 nm +3.3 v sfp optical transceiver for gigabit ethernet hfbr-5912e: 850 nm +3.3 v sff optical transceiver for gigabit ethernet hdmp-1636a: 1.25 gbps trx family of serdes ic hfbr-0534: sfp evaluation kit
2 module diagrams figure 1 illustrates the major functional components of the HBCU-5710R. the 20-pin connection diagram of module printed circuit board of the module is shown in figure 2. figure 3 depicts the pin assignment of the mdi (rj45 jack). figure 7 depicts the external configuration and dimensions of the module. installation the HBCU-5710R can be installed in or removed from any multisource agreement (msa) compliant small form pluggable port whether the host equipment is operating or not. the module is simply inserted, small end first, under finger-pressure. controlled hot-plugging is ensured by design and by 3- stage pin sequencing at the electrical interface to the host board. the module housing makes initial contact with the host board emi shield, mitigating potential damage due to electro-static discharge (esd). the module pins sequentially contact the (1) ground, (2) power, and (3) signal pins of the host board surface mount connector. this printed circuit board card-edge connector is depicted in figure 2. a b c d magnetics rj45 adapter eeprom serdes/ dsp tx_data rx_data tx_disable tx_fault rx_los rate_select nc mod_def2 mod_def1 mod_def0 figure 1: transceiver functional diagram note: tx_fault and rate_select not used. figure 2: 20-pin connection diagram of module printed circuit board 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 v ee t td- td+ v ee t v cc t v cc r v ee r rd+ rd- v ee r v ee t tx_fault tx_disable mod-def(2) mod-def(1) mod-def(0) rate select los v ee r v ee r top of board bottom of board (as viewed thru top of board) figure 3: mdi ( rj 45 jack) pin assignment pin 1 pin 8
3 serial identification (eeprom) the HBCU-5710R complies with an industry standard multisource agreement that defines the serial identification protocol. this protocol uses the 2-wire serial cmos eeprom protocol of the atmel at24c01a or equivalent. the contents of the HBCU-5710R serial id memory are defined in table 3 as spec ified in the sfp msa. controller and data i/o data i/os are designed to accept industry standard differential signals. in order to reduce the number of passive components required on the customers board, agilent has included the functionality of the transmitter bias resistors and coupling capacitors within the module. the transceiver is compatible with an ac-coupled configuration and is internally terminated. figure 1 depicts the functional diagram of the HBCU-5710R. caution should be taken into account for the proper interconnection between the supporting physical layer integrated circuits and the HBCU-5710R. figure 4 illustrates the recommended interface circuit. several control data signals and timing diagrams are implemented in the module and are depicted in figure 6. application support evaluation kit to help you in your preliminary transceiver evaluation, agilent offers a 1.25 gbd gigabit ethernet evaluation board. this board will allow testing of the electrical parameters of transceiver. please contact your local field sales representative for availability and ordering details. reference designs reference designs for the hbcu- 5710r electrical transceiver and the hdmp-1636a physical layer ic are available to assist the equipment designer. figure 4 depicts a typical application configuration, while figure 5 depicts the msa power supply filter circuit design. please contact your local field sales engineer for more information regarding application tools.
4 regulatory compliance see table 1 for transceiver regulatory compliance performance. the overall equipment design will determine the certification level. the transceiver performance is offered as a figure of merit to assist the designer. electrostatic discharge (esd) there are two conditions in which immunity to esd damage is important. table 1 documents our immunity to both of these conditions. the first condition is during handling of the transceiver prior to insertion into the transceiver port. to protect the transceiver, it is important to use normal esd handling precautions. these precautions include using grounded wrist straps, work benches, and floor mats in esd controlled areas. the esd sensitivity of the HBCU-5710R is compatible with typical industry production environments. the second condition is static discharges to the exterior of the host equipment chassis after installation. to the extent that the rj45 connector interface is exposed to the outside of the feature test method performance electrostatic discharge (esd) to the electrical pins mil-std-883c, method 3015.4 jedec/ eia jesd22-a114-a class 2 (2000 volts) electrostatic discharge (esd) to the rj 45 connector receptacle variation of iec 61000-4-2 typically withstand 15 kv ( air discharge), 8 kv ( contact) without damage when the rj 45 connector receptacle is contacted by a human body model probe. electromagnetic interference (emi) fcc part 15 class b cenelec en55022 class b (cispr 22a) vcci class 1 system margins are dependent on customer board and chassis design. immunity variation of iec 61000-4-3 typically shows a negligible effect from a 10 v/m field swept from 80 to 1000 mhz applied to the transceiver without a chassis enclosure. component recognition underwriters laboratories and canadian standards association joint component recognition for information technology equipment including electrical business equipment ul file # e173874 tuv file # r 72031300 page 2 table 1: regulatory compliance host equipment chassis, it may be subject to system-level esd requirements. the esd performance of the HBCU-5710R exceeds typical industry standards. immunity equipment hosting the hbcu- 5710r modules will be subjected to radio-frequency electromagnetic fields in some environments. the transceivers have good immunity to such fields due to their shielded design. electromagnetic interference (emi) most equipment designs utilizing these high-speed transceivers from agilent will be required to meet the requirements of fcc in the united states, cenelec en55022 (cispr 22a) in europe and vcci in japan. the metal housing and shielded design of the HBCU-5710R minimize the emi challenge facing the host equipment designer. these transceivers provide superior emi performance. this greatly assists the designer in the management of the overall system emi performance. flammability the HBCU-5710R electrical transceiver housing is made of metal and high strength, heat resistant, chemically resistant, and ul 94v-0 flame retardant plastic. caution there are no user serviceable parts nor any maintenance required for the HBCU-5710R. tampering with or modifying the performance of the HBCU-5710R will result in voided product warranty. it may also result in improper operation of the HBCU-5710R circuitry, and possible overstress of the rj 45 connector. device degradation or product failure may result. connection of the HBCU-5710R to a non-approved other 1000base-t module, operating above the recommended absolute maximum conditions or operating the HBCU-5710R in a manner inconsistent with its design and function may result in hazardous radiation exposure and may be considered an act of modifying or manufacturing an electrical module product.
5 v_supply 10 uf 0.1 uf 1 uh 1 uh 0.1 uf 10 uf 0.1 uf ordering information please contact your local field sales engineer or one of agilents franchised distributors for ordering information. for technical information, please visit agilents web page at www.agilent.com or contact agilent semiconductor products customer response center at 1- 800-235-0312. for information related to the msa visit www.schelto.com/sfp/index.html figure 4: typical application configuration note: inductors must have less than 1 ohm series resistance per msa. figure 5: msa recommended power supply filter protocol ic hdmp- 1636a v_supply tx[0:9] rx[0:9] 10 uf 0.1 uf 1 uh 1 uh 0.1 uf 10 uf 0.1 uf vcc_t vcc_r 4.7 k tx_disable tx_fault td+ td- rd+ rd- 100 rx_los ref clk v_supply mod_def 1 mod_def 2 mod_def 0 4.7 k 4.7 k 4.7 k 4.7 k 0.01 uf HBCU-5710R eeprom rj45 jack & magnetics cat5 cable 0.01 uf 0.01 uf 0.01 uf phy ic 100 50 50
6 table 2: 20-pin connection diagram description notes: 1. tx fault is not used and is always tied to ground. 2. tx disable as described in the msa is not applicable to the 1000base-t module, but is used for convenience as an input to res et the internal asic. this pin is pulled up within the module with a 4.7 k w resistor. low (0 ? 0.4v): transceiver on between (0.4v and 2.0 v): undefined high (2.0 ? 3.465 v): transceiver in reset state open: transceiver in reset state 3. mod-def 0,1,2. these are the module definition pins. they should be pulled up with a 4.7-10 k w resistor on the host board to a supply less than v cc t + 0.3 v or v cc r + 0.3 v. mod-def 0 is grounded by the module to indicate that the module is present mod-def 1 is clock line of two wire serial interface for optional serial id mod-def 2 is data line of two wire serial interface for optional serial id 4. los (loss of signal) is not used and is always tied to ground in figure 4. 5. rd-/+: these are the differential receiver outputs. they are ac coupled 100 w differential lines which should be terminated with 100 w differential at the user serdes. the ac coupling is done inside the module and is thus not required on the host board. the voltage swing on these lines will be between 370 and 2000 mv differential (185 ? 1000 mv single ended) when properly terminated. these levels are compatible with cm l and lvpecl voltage swings. 6. v cc r and v cc t are the receiver and transmitter power supplies. they are defined as 3.3 v 5% at the sfp connector pin. the maximum su pply current is 370 ma and the associated in-rush current will typically be no more than 30 ma above steady state after 500 nanoseco nds. 7. td-/+: these are the differential transmitter inputs. they are ac coupled differential lines with 100 w differential termination inside the module. the ac coupling is done inside the module and is thus not required on the host board. the inputs will accept differential swings of 500 ? 2400 mv (250 ? 1200 mv single ended), though it is recommended that values between 500 and 1200 mv differential (250 ? 600 mv single ended) be used for best emi performance. these levels are compatible with cml and lvpecl voltage swings. pin name function/description msa notes 1v ee t transmitter ground 2 tx fault transmitter fault indication - high indicates a fault note 1 3 tx disable transmitter disable - module disables on high or open note 2 4 mod-def2 module definition 2 - two wire serial id interface note 3 5 mod-def1 module definition 1 - two wire serial id interface note 3 6 mod-def0 module definition 0 - grounded in module note 3 7 rate select not connected 8 los loss of signal - high indicates loss of signal note 4 9v ee rreceiver ground 10 v ee rreceiver ground 11 v ee rreceiver ground 12 rd- inverse received data out note 5 13 rd+ received data out note 5 14 v ee rreceiver ground 15 v cc r receiver power - 3.3 v +/- 5% note 6 16 v cc t transmitter power - 3.3 v +/- 5% note 6 17 v ee t transmitter ground 18 td+ transmitter data in note 7 19 td- inverse transmitter data in note 7 20 v ee t transmitter ground
7 absolute maximum ratings recommended operating conditions transceiver electrical characteristics (t c = 0 c to +70 c, v cc t, r = 3.3 v 5%) notes: 1. absolute maximum ratings are those values beyond which damage to the device may occur if these limits are exceeded for other than a short period of time. see reliability data sheet for specific reliability performance. 2. between absolute maximum ratings and the recommended operating conditions functional performance is not intended, device reli ability is not implied, and damage to the device may occur over an extended period of time. 3. recommended operating conditions are those values outside of which functional performance is not intended, device reliability is not implied, and damage to the device may occur over an extended period of time. see reliability data sheet for specific reliability performanc e later when it is ready. 4. 100 m cat 5 cable. 5. msa-specified filter is required on the host board to achieve psnr performance over the frequency range 10 hz to 2 mhz. 6. icc max at 3.1 v, +70 c. 7. lvttl, external 4.7-10 k w pull-up resistor required. parameter symbol minimum typical maximum unit notes storage temperature t s -40 +75 c note 1 case temperature t c -40 +75 c note 1, 2 relative humidity rh 5 95 % note 1 module supply voltage v cc t,r -0.5 3.6 v note 1, 2 data/control input voltage v i -0.5 v cc vnote 1 sense output current - mod-def 2 5.0 ma parameter symbol minimum typical maximum unit notes case temperature t c 0 +70cnote 3 module supply voltage v cc t,r 3.135 3.3 3.465 v note 3 data rate 1.25 gb/s note 3 parameter symbol minimum typical m aximum unit notes bit error rate ber 10 -10 note 4 ac electrical characteristics power supply noise rejection (peak-peak) psnr 100 mv note 5 dc electrical characteristics module supply current i cc 370 ma note 6 power dissipation p diss 1150 mw sense outputs: mod-def 2 v oh 2.4 v cc t,r + 0.3 v n ote 7 v ol 0.4 v control inputs: tran sm itter d isable mod-def 1,2 v ih 2.0 v cc vnote 7 v il 00.8v control inputs: tran sm itter d isable (tx_disable) v ih 2.0 v cc v v il 00.4v
8 transmitter and receiver electrical characteristics (t c = 0 c to +70 c, v cc t, r = 3.3 v 5%) transceiver timing characteristics (t c = 0 c to +70 c, v cc t, r = 3.3 v 5%) notes: 1. internally ac coupled and terminated (100 ohm differential). these levels are compatible with cml and lvpecl voltage swings. 2. internally ac coupled with an external 100 ohm differential load termination. 3. represents nominal output voltage. user may change values through register 26.2:0. please refer to table 19 for output setti ngs. 4. 20%-80% rise and fall times measured from the module?s internally generated gigabit ethernet idle pattern at 1.25 gbps. 5. tx disable function as described in the sfp msa is not used in the 1000base-t module. 6. time from rising edge of tx disable until link comes down. 7. time from falling edge of tx disable until auto-negotiation starts. parameter symbol minimum typical maximum unit notes data input: transmitter differential input voltage (td +/- ) v i 500 2400 mv note 1 data output : receiver differential output voltage (rd +/-) v o 600 800 mv note 2 note 3 receive data rise & fall times (receiver) trf 250 ps note 4 parameter symbol minimum typical maximum unit notes tx disable assert time t_off na note 5 tx disable negate time t_on na note 5 module reset assert time t_off_rst 10 s note 6 module reset negate time t_on_rst 300 s note 7 time to initialize t_init 300 ms tx fault assert time t_fault na tx disable to reset t_reset na rate select change time t_ratesel na serial id clock rate f_serial_clock 100 khz
9 v cc > 3.15 v t_init power saving (tx_disable) transmitted signal (auto-negotiation begins) t-init: module hot-plugged or voltage applied after insertion, when tx_disable is negated figure 6: transceiver timing diagrams (module installed except where noted) v cc > 3.15 v t_init tx_disable transmitted signal (auto-negotiation begins) t-init: voltage applied when tx_disable is asserted t_on_rst t_off_rst tx_disable transmitted signal (auto-negotiation begins on rising edge) t_off_rst & t_on_rst: tx_disable (reset) asserted then de-asserted t_on_rst
10 table 3: eeprom serial id memory contents at address a0 notes: 1. address 68-83 specify a unique identifier. 2. address 84-91 specify the date code. 3. addresses 63 and 95 are check sums. address 63 is the check sum for bytes 0-62 and address 95 is the check sum for bytes 64- 94. address hex ascii address hex ascii address hex ascii address hex ascii 003 4048h68note 1 9620 104 4142b69note 1 9720 200 4243c70note 1 9820 300 4355u71note 1 9920 4 00 44 2d - 72 note 1 100 20 5 00 45 35 5 73 note 1 101 20 6 08 46 37 7 74 note 1 102 20 7 00 47 31 1 75 note 1 103 20 8 00 48 30 0 76 note 1 104 20 9 00 49 52 r 77 note 1 105 20 10 00 50 20 78 note 1 106 20 11 01 51 20 79 note 1 107 20 12 0d 52 20 80 note 1 108 20 13 00 53 20 81 note 1 109 20 14 00 54 20 82 note 1 110 20 15 00 55 20 83 note 1 111 20 16 00 56 20 84 note 2 112 20 17 00 57 20 85 note 2 113 20 18 64 58 20 86 note 2 114 20 19 00 59 20 87 note 2 115 20 20 41 a 60 00 88 note 2 116 20 21 47 g 61 00 89 note 2 117 20 22 49 i 62 00 90 20 118 20 23 4c l 63 note3 91 20 119 20 24 45 e 64 00 92 00 120 20 25 4e n 65 10 93 00 121 20 26 54 t 66 00 94 00 122 20 27 20 67 00 95 note 3 123 20 28 20 124 20 29 20 125 20 30 20 126 20 31 20 127 20 32 20 33 20 34 20 35 20 36 00 37 00 38 30 39 d3
11 internal asic registers the asic (or phy, for physical layer ic) in the transceiver module contains 32 registers. each register contains 16 bits. the registers are summarized in table 4 and detailed in tables 5 through 22. each bit is either read only (ro) or read/write (r/w). some bits are also described as latch high (lh) or latch low (ll) and/or self clearing (sc). register description 0control 1 status 2-3 n/a for sfp module 4 auto-negotiation advertisement 5 auto-negotiation link partner ability 6 auto-negotiation expansion 7 auto-negotiation next page transmit 8 auto-negotiation link partner received next page 9 master-slave control register 10 master-slave status register 11-15 n/a for sfp module 16 extended control 1 17 extended status 1 18-19 n/a for sfp module 20 extended control 2 21 receive error counter 22 cable diagnostic 1 23 n/a for sfp module 26 extended control 3 27 extended status 2 28 cable diagnostic 2 29-30 specific function registers 31 n/a for sfp module the registers are accessible through the 2-wire serial cmos eeprom protocol of the atmel at24c01a or equivalent. the address of the phy is 1010110x, where x is the r/w bit. each registers address is 000yyyyy, where yyyyy is the binary equivalent of the register number. write and read operations must send or receive 16 bits of data, so the multi- page access protocol must be used. table 4. summary of internal ic registers at address ac
12 table 5: register 0 (control) bit name description hardware reset software reset details 0.15 r/w reset 1 = phy reset 0 = normal operation 0 self-clearing performs software reset 0.14 r/w loopback 1 = enable 0 = disable 0 0 serial data in on rd+/- is deserialized, then reserialized and sent out on td+/- 0.13 r/w speed selection (lsb) 0 = 1000 mb/s 0 update paired with bit 0.6. other settings indicate different speeds, but the module will not function at speeds other than 1000 mb/s. this bit is only meaningful if bit 0.12 is 0. 0.12 r/w auto-negotiation enable 1 = enable 0 = disable 0 update changes to this bit take effect after software reset. 0.11 r/w power down 1 = power down 0 = normal operation 00 0.10 r/w isolate 1 = isolate 0 = normal operation 00 0.9 r/w/sc restart auto- negotiation 1 = restart auto-negotiation process 0 = normal operation 0 self-clearing 0.8 r/w duplex mode 1 = full duplex 0 = half duplex 1 update this bit is only meaningful if 0.12 is 0. 0.7 r/w collision test 1 = enable col signal test 0 = disable col signal test 00 0.6 r/w speed selection (msb) 1 = 1000 mb/s 1 update paired with bit 0.13. other settings indicate different speeds, but the module will not function at speeds other than 1000 mb/s. this bit is only meaningful if bit 0.12 is 0. 0.5:0 r/w n/a to sfp module 000000 000000
13 table 6: register 1 (status) table 7. register 4 (auto-negotiation advertisement) bit name description hardware reset software reset details 1.15:9 ro n/a to sfp module 0000000 0000000 1.8 ro extended status 1 = extended status information in register 15 11 always 1 1.7 ro n/a to sfp module 0 0 1.6 ro mf preamble suppression 1 = phy will accept management frames with preamble suppressed. 11 always 1 1.5 ro auto-negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 00 1.4 ro/lh remote fault 1 = remote fault condition detected 0 - no remote fault condition detected 00 1.3 ro auto-negotiation ability 1 = module is able to perform auto- negotiation 0 = module is unable to perform auto- negotiation 11 1.2 ro/ll link status 1 = link is up 0 = link is down 00 1.1 ro/lh jabber detect 1 = jabber condition detected 0 = no jabber condition detected 00 1.0 ro extended capability 1 = extended register capabilities 1 1 always 1 bit name description hardware reset software reset details 4.15:14 r/w n/a to sfp module 00 00 when writing to register 4, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module. 4.13 r/w remote fault 1 = remote fault bit is set 0 = no remote fault 0 retain this bit takes effect after auto- negotiation is restarted, either via bit 0.9 or because the link goes down. 4.12 r/w n/a to sfp module 0 retain 4.11:10 r/w pause encoding 11 = both asymmetric pause and symmetric pause toward local device 10 = asymmetric pause toward link partner 01 = symmetric pause 00 = no pause 11 retain this bit takes effect after auto- negotiation is restarted, either via bit 0.9 or because the link goes down. 4.9:5 r/w n/a to sfp module 00000 00000 4.4:0 ro ieee 802.3 selector field 00001 00001 set per ieee standard.
14 table 8: register 5 (auto-negotiation link partner ability) table 9: register 6 (auto-negotiation expansion) bit name description hardware reset software reset details 5.15 ro next page 1 = link partner advertises next page ability 0 = link partner does not advertise next page ability 00 5.14 ro acknowledge 1 = link partner acknowledges receiving link code word from module 0 = link partner does not acknowledge receiving link code word from module 00 5.13 ro remote fault 1 = link partner has a remote fault 0 = link partner does not have a remote fault 00 5.12 ro n/a to sfp module 0 0 5.11:10 ro pause encoding 11 = asymmetric pause and symmetric pause toward local device 10 = asymmetric pause toward link partner 01 = symmetric pause 00 = no pause 00 00 5.9:5 ro n/a to sfp module 00000 00000 5.4:0 ro ieee 802.3 selector field 00000 00000 set per ieee standard. bit name description hardware reset software reset details 6.15:5 ro n/a to sfp module 00000000000 00000000000 6.4 ro parallel detection fault 1 = a fault has been detected via the parallel detection function 0 = a fault has not been detected via the parallel detection function 0 0 this register is not valid until auto-negotiation is complete, as indicated by bit 1.5. 6.3 ro link partner next page able 1 = link partner is next page able 0 = link partner is not next page able 0 0 see note in bit 6.4. 6.2 ro next page able 1 = local device is next page able 0 = local device is not next page able 1 1 see note in bit 6.4. 6.1 ro/lh page received 1 = a new page has been received 0 = a new page has not been received 0 0 see note in bit 6.4. 6.0 ro link partner auto- negotiation able 1 = link partner is auto-negotiation able 0 = link partner is not auto-negotiation able 0 0 see note in bit 6.4.
15 table 10: register 7 (auto-negotiation next page transmit register) table 11: register 8 (auto-negotiation link partner received next page) bit name description hardware reset software reset details 7.15 r/w next page 1 = additional next pages to follow 0 = last page 00 7.14 ro n/a to sfp module 0 0 7.13 r/w message page 1 = message page 0 = unformatted page 11 7.12 r/w acknowledge 2 1 = will comply with message 0 = will not comply with message 00 7.11 ro toggle 1 = previous value of the toggle bit was 00 = previous value of the toggle bit was 1 00 7.10:0 r/w message/unformatted code field 00000000001 00000000001 bit name description hardware reset software reset details 8.15 ro next page 1 = additional next pages to follow 0 = last page 00 8.14 ro acknowledge 1 = acknowledge received 0 = acknowledge not received 00 8.13 ro message page 1 = message page 0 = unformatted page 00 8.12 ro acknowledge 2 1 = will comply with message 0 = will not comply with message 00 8.11 ro toggle 1 = previous value of the toggle bit was 00 = previous value of the toggle bit was 1 00 8.10:0 ro message/unformatted code field 00000000000 00000000000
16 table 12: register 9 (master-slave control) bit name description hardware reset software reset details 9.15:13 r/w tr a ns mi tt e r tes t mo d e 00 0 = n o r m al o p er a t io n 001 = transmit waveform test 010 = transmit jitter test in master mode 011 = transmit jitter test in slave mode 000 000 the module enters test modes when mdi crossover is first disabled via bits 16.6:5. 9.12 r/w master-slave manual config enable 1 = enable master-slave manual configuration value in register 9.11 0 = disable master-slave manual configuration value in register 9.11 0 retain this bit takes effect after auto- negotiation is restarted via bit 0.9. 9.11 r/w master-slave config value 1 = configure phy as master during master-slave negotiation 0 = configure phy as slave during master-slave negotiation 1 retain this bit takes effect after auto- negotiation is restarted via bit 0.9. this bit is ignored unless bit 9.12 is 1. 9.10 r/w port type 1 = prefer phy as master (multiport) 0 = prefer phy as slave (single port) 1 retain this bit takes effect after auto- negotiation is restarted via bit 0.9. this bit is ignored unless bit 9.12 is 0. 9.9 r/w 1000base-t full duplex 1 = advertise phy is 1000base-t full duplex capable 0 = advertise phy is not 1000base-t full duplex capable 1 retain this bit takes effect after auto- negotiation is restarted via bit 0.9. 9.8 r/w 1000base-t half duplex 1 = advertise phy is 1000base-t half duplex capable 0 = advertise phy is not 1000base-t half duplex capable 0 retain this bit takes effect after auto- negotiation is restarted via bit 0.9. 9.7:0 ro n/a to sfp module 00000000 00000000
17 table 13: register 10 (master-slave status) table 14: register 16 (extended control 1) bit name description hardware reset software reset details 10.15 ro/lh/sc master-slave configuration fault 1 = master-slave configuration fault detected 0 = no master-slave configuration fault detected 0 0 this bit is cleared each time that this register is read. this bit clears on auto-negotiation enable or auto-negotiation complete. this bit is set if the number of failed master- slave resolutions reaches 7. this bit is set if both phy's are forced to master's or slave's at the same time using bits 9.12 and 9.11. 10.14 ro master-slave configuration resolution 1 = local phy configuration resolved to master 0 = local phy configuration resolved to slave 00 10.13 ro local receiver status 1 = local receiver ok 0 = local receiver not ok 00 10.12 ro remote receiver status 1 = remote receiver ok 0 = remote receiver not ok 00 10.11 ro link partner full duplex 1 = link partner is capable of 1000base-t full duplex 0 = link parnter is not capable of 1000base-t full duplex 0 0 this bit is valid only when the page received bit (6.1) is set to 1. 10.10 ro link partner half duplex 1 = link partner is capable of 1000base-t half duplex 0 = link parnter is not capable of 1000base-t half duplex 0 0 this bit is valid only when the page received bit (6.1) is set to 1. 10.9:8 n/a to sfp module 00 00 10.7:0 ro/sc idle error count counts errors when receiving idle patterns. 00000000 00000000 these bits do not roll-over when they are all one's. bit name description hardware reset software reset details 16.15:7 r/w n/a to sfp module 000000000 retain (15:10, 7) or update (9:8) when writing to register 16, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module. 16.6:5 r/w mdi crossover mode 00 = manual mdi configuration 01 = manual mdix configuration 10 = n/a to sfp module 11 = enable automatic crossover 11 update changes to this bit take effect after software reset. 16.4:0 r/w n/a to sfp module 11000 retain (2:0) or update (4:3) when writing to register 16, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module.
18 table 15: register 17 (extended status 1) bit name description hardware reset software reset details 17.15:14 ro speed 10 = 1000 mbps 0 retain this bit is only valid after bit 17.11 is set. 17.13 ro duplex 1 = full duplex 0 = half duplex 0 retain this bit is only valid after bit 17.11 is set. 17.12 ro/lh page received 1 = page received 0 = page not received 00 17.11 ro speed and duplex resolved 1 = resolved 0 = speed not resolved 0 0 this bit is set when auto- negotiation is either completed or disabled. 17.10 ro link 1 = link up 0 = link down 00 17.9:7 ro cable length 000 = < 50 m 001 = 50 - 80 m 010 = 80 - 110 m 011 = 110 - 140 m 100 = > 140 m 000 000 17.6 ro mdi crossover status 1 = crossover 0 = no crossover 0 0 crossover means that pairs a+/- (pins 1 & 2 on the rj45 jack) and b+/- (pins 3 & 6) are interchanged and c+/- (pins 4 &5) and d+/- (pins 7 & 8) are interchanged. this bit is only valid after bit 17.11 is set. 17.5:4 ro n/a to sfp module 00 00 17.3 ro mac transmit pause enabled 1 = transmit pause enabled 0 = transmit pause disabled 0 0 this bit reflects the capability of the mac to which the module is connected on the serial side. this bit is only valid after bit 17.11 is set. 17.2 ro mac receive pause enabled 1 = receive pause enabled 0 = receive pause disabled 0 0 this bit reflects the capability of the mac to which the module is connected on the serial side. this bit is only valid after bit 17.11 is set. 17.1 ro polarity 1 = polarity reversed 0 = polarity not reversed 0 0 this bit is set if any of the four twisted pairs have the + and - wires reversed. 17.0 ro jabber 1 = jabber detected 0 = no jabber detected 0
19 table 16: register 20 (extended control 2) table 17: register 21 (receive error counter) table 18: register 22 (cable diagnostic 1) bit name description hardware reset software reset details 20.15 ro link down on no idles 1 = link lock lost 0 = link lock intact 0 0 if idle patterns are not seen within 1 ms, link lock is lost and link is brought down. 20.14:4 r/w n/a to sfp module 00011000110 0001100110 when writing to register 20, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module. 20.3 r/w clause 37 auto- negotiation enable 0 = disable base-x auto-negotiation 1 = enable base-x auto-negotiation 1 update changes to this bit take effect after software reset. 20.2:0 r/w n/a to sfp module 000 000 when writing to register 20, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module. bit name description hardware reset software reset details 21.15:0 ro/sc receive errors counts errors received on the 1000base-t side 0 0 these bits do not roll-over when they are all one's. bit name description hardware reset software reset details 22.7:0 r/w base-x/ base-tauto- negotiation register select 00000000= registers 0-1, 14-8 and 17- 19 are base-t values00000001= registers 0-1, 14-8 and 17-19 are base- x values 00000000 retain overlapping usage with vct (see below) 22.15:8 ro n/a to sfp module 22.1:0 r/w mdi pair select 00 = pins 1 & 2 (channel a) 01 = pins 3 & 6 (channel b) 10 = pins 4 & 5 (channel c) 11 = pins 7 & 8 (channel d) 00 retain for vct results, choose the twisted pair on which register 28 will display.
20 table 19: register 26 (extended control 3) table 20: register 27 (extended status 2) bit name description hardware reset software reset details 26.15:8 ro n/a to sfp module 00000000 retain 26.7:3 r/w n/a to sfp module 00001 update when writing to register 26, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module. 26.2:0 r/w rd+/- output amplitude 000 = 0.50 v 001 = 0.55 v 010 = 0.60 v 011 = 0.65 v 100 = 0.70 v 101 = 0.75 v 110 = 0.80 v 111 = 0.85 v 010 retain all voltages measured peak-to- peak into a 100-ohm load. output amplitude values are approximate. bit name description hardware reset software reset details 27.15:13 ro/sc n/a to sfp module 100 update (27.15), retain (27.14:13) when writing to register 27, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module. 27.12 r/w 1000base-x auto- negotiation bypass enable 1 = enabled 0 = disabled 1 update if enabled, base-x link will come up after 200 ms even if base-x auto-negotiation fails. when writing to register 27, be sure to preserve the values of this bit. changes to this value can interrupt the normal operation of the sfp module. 27.11 ro 1000base-x auto- negotiation bypass status 1 = base-x auto-negotiation failed and base-x link came up becase bypass mode timer expired 0 = base-x link came up bacause regular base-x auto-negotiation was completed 0 retain see bit 27.12. 27.10:0 r/w n/a to sfp module 00010001000 update when writing to register 27, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module.
21 table 21: register 28 (cable diagnostic 2) table 22: registers 29-30 (specific function registers) specific function registers are used to enable special functions such as packet generator, crc error check and external loopback. bit name description hardware reset software reset details 28.15 r/w enable cable diagnostic test 1 = enable test 0 = disable test 0 0 the test can only be performed when the link is down. if the link partner is trying to auto- negotiate or if the link partner is sending out idle link pulses, the test will proceed. 28.14:13 ro status 11 = test fail 10 = open detected in twisted pair 01 = short detected in twisted pair 00 = no short or open detected in twisted pair 00 00 the twisted pair under test is specified in register 22. 28.12:8 ro reflected magnitude 11111 = 1 v 10000 = 0 v 00000= -1 v 00000 00000 the twisted pair under test is specified in register 22. 28.7:0 ro distance distance to the short or open 00000000 00000000 the distance is given in meters by 13/16 * (decimal equivalent of 28.7:0) + 32 .the twisted pair under test is specified in register 22. if no short or open is detected, these bits are 0's.
22 figure 7a: module drawing (dimensions in millimeter) 14.10 +.10 14.0 max 16.60 +.30 14.60 +.30 14.10 +.30 45.00 +.40 41.80 +.15 34.50 +.20 9.2 +.10 8.50 +.10 case temperature probe point
23 figure 7b. assembly drawing
24 figure 7c. sfp host board mechanical layout
www.agilent.com/ semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 1 0800 650 0017 hong kong: (+65) 6756 2394 india, australia, new zealand: (+65) 6755 1939 japan: (+81 3) 3335-8152(domestic/international), or 0120-61-1280(domestic only) korea: (+65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (+65) 6755 2044 taiwan: (+65) 6755 1843 data subject to change. copyright ? 2004 agilent technologies, inc. february 12, 2004 5989-0570en

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